Method and apparatus to reduce noise in ct data acquisition systems

ABSTRACT

The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.

CROSS REFERENCES TO RELATED APPLICATIONS

This application claims priority from India provisional patentapplication No. 1146/CHE/2014 filed on Mar. 6, 2014 which is herebyincorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure is generally related to medical diagnosticdevices, and more particularly to reducing noise in computed tomography(CT) data acquisition systems.

BACKGROUND

Computed tomography (CT) is a medical imaging technique that producesthree-dimensional images of internal human body parts from a largeseries of two-dimensional X-ray images (called profiles) taken in asingle-axis rotating structure called a gantry. When compared to aconventional X-ray radiograph, which is an image of many planessuperimposed on each other, a CT image exhibits significantly improvedcontrast.

With the advent of diagnostic imaging systems like CT, where complex andintensive image processing is required, semiconductors play a veryimportant role in developing systems with increased density, flexibilityand high performance. The helical or spiral CT machines that use fastercomputer systems and optimized software can continuously process thecross-section images while the object passes through the gantry at aconstant speed.

X-ray slice data is generated using an X-ray source that rotates aroundthe object, with X-ray detectors positioned on the opposite side of thecircle from the X-ray source. Many data scans are taken progressively asthe patient/object is gradually passed through the gantry. Ascintillator receives x-rays attenuated by the patient and generateslight. A data acquisition system includes a plurality of detectors orchannels.

A detector receives the light form the scintillator and generates acorresponding current signal which is further converted to a digitalsignal. Since, the x-rays emitted by the x-ray source undergoattenuation while passing through the patient, not all the detectors ofthe plurality of detectors receive a large signal. Most of the detectorsreceive a very small attenuated signal (less than 10-15% of the signalemitted by the x-ray source).

Traditional, data acquisition systems provide a fixed gain for all thedetectors of the plurality of detectors. This causes noise to be highfor all the channels, and even for those channels which receive the verysmall attenuated signal.

SUMMARY

According to an aspect of the disclosure, a circuit is disclosed. Thecircuit includes an integrator that generates an integrated signal inresponse to a current signal. A comparator is coupled to the integratorand receives the integrated signal and a primary reference voltagesignal. The comparator generates a feedback signal. A switched capacitornetwork is coupled across the integrator. The feedback signal activatesthe switched capacitor network.

BRIEF DESCRIPTION OF THE VIEWS OF DRAWINGS

FIG. 1 illustrates a circuit;

FIG. 2 illustrates a circuit, according to an embodiment;

FIG. 3 is a timing diagram to illustrate the operation of the circuitillustrated in FIG. 2, according to an embodiment;

FIG. 4 is a graph to illustrate the operation of the circuit illustratedin FIG. 2, according to an embodiment;

FIG. 5 illustrates a circuit, according to an embodiment;

FIG. 6 illustrates a method for generating a digital signal from acurrent signal, according to an embodiment; and

FIG. 7 illustrates an imaging system, according to an embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1 illustrates a circuit 100. The circuit 100 includes a photodiode102, an integrator 115, a compensation capacitor Cc 122, a secondarytransconductor 140 and an analog to digital converter (ADC) 150. Thecircuit 100 also includes a set of first switches illustrated as S1 120,a set of second switches illustrated as S2 124, a set of third switchesillustrated as S3 126, a set of fourth switches illustrated as S4 128and a set of fifth switches illustrated as S5 134.

The photodiode 102 includes a sensor 104 and an associated capacitanceCs 106. The integrator 115 is coupled to the photodiode 102 through thefirst switch S1 120. The integrator 115 includes a primarytransconductor 110 with an inverting terminal 114 and a non-invertingterminal 116. The photodiode 102 is coupled to the inverting terminal114 of primary transconductor 110. A non-inverting terminal 116 of theprimary transconductor 110 is coupled to a ground terminal. A secondswitch S2 is coupled between the inverting terminal 114 and thenon-inverting terminal 116 of the primary transconductor 110.

A feedback capacitor C_(F) 112 is coupled between the inverting terminal114 and a first output terminal 118 of the primary transconductor 110.The feedback capacitor C_(F) 112 is coupled to the inverting terminal114 through the third switch S3 126, and the feedback capacitor C_(F)112 is coupled to the first output terminal 118 through the third switchS3 126.

The feedback capacitor C_(F) 112 is also coupled to a reference voltagesignal Vref 136 and a ground terminal GND through fourth switches S4128. The ADC 150 is coupled across the feedback capacitor C_(F) 112through the fifth switches S5 134. The compensation capacitor Cc 122 iscoupled to the first output terminal 118 of the primary transconductor110 through the first switch S1 120. The compensation capacitor Cc 122is coupled to the reference voltage signal Vref 136 through the secondswitch S2 124.

The secondary transconductor 140 receives the reference voltage signalVref 136 at a first input terminal 144. A second input terminal 146 ofthe secondary transconductor 140 is coupled to a first capacitor C_(A)142. The other end of first capacitor C_(A) 142 is coupled to the groundterminal. The second input terminal 146 is coupled to an output terminal148 of the secondary transconductor 140 through the second switch S2124. The output terminal 148 of the secondary transconductor 140 iscoupled to the first output terminal 118 of the primary transconductor110.

The operation of the circuit 100 illustrated in FIG. 1 is explained now.The photodiode 102 receives light and generates a corresponding currentsignal. The sensor 104 receives the light and the associated capacitanceCs 106 stores a charge corresponding to the received light. The circuit100 operates in a reset phase, an integration phase and a sample phase.

In the reset phase, the set of second switches S2 124 and the set offourth switches S4 128 are closed. When the switch S2 124 is closed, theinverting terminal 114 and the non-inverting terminal 116 of the primarytransconductor 110 are coupled to the ground terminal. An offsetassociated with the primary transconductor 110 will result in a currentflowing from the first output terminal 118 of the primary transconductor110.

A corresponding voltage develops at the second input terminal 146 of thesecondary transconductor 140 and is stored in the first capacitor C_(A)142. Since, the fourth switch S4 128 is closed, the feedback capacitorC_(F) 112 is charged to the reference voltage signal Vref 136. Also, thecompensation capacitor Cc 122 is charged to the reference voltage signalVref 136.

In the integration phase, the set of first switches S1 120 and the setof third switches S3 126 are closed, while other switches are in openstate. The photodiode 102 generates the current signal based on thereceived light. The integrator 115 receives the current signal from thephotodiode 102 at the inverting terminal 114 of the primarytransconductor 110.

The integrator 115 generates an integrated signal at the first outputterminal 118 of the primary transconductor 110. The secondarytransconductor 140 compensates the offset associated with the primarytransconductor 110. The integrator 115 integrates the current signal onthe feedback capacitor C_(F) 112. The feedback capacitor C_(F) 112discharges through the photodiode 102. At the end of integration phase,a voltage across the feedback capacitor C_(F) 112 is a sampled voltage.

In the sample phase, the set of fifth switches S5 134 are closed, whileother switches are in open state. The ADC 150 measures the sampledvoltage across the feedback capacitor C_(F) 112. The ADC 150 generates adigital signal 154 from the sample voltage.

A total noise of the circuit 100 is defined as:

N=N _(reset) +N _(int) +N _(adc)  (1)

where, N_(reset) is a noise of the circuit 100 in the reset phase,N_(int) is a noise of the circuit 100 in the integration phase, andN_(adc) is a noise of the circuit 100 in the sample phase.

The noise in the reset phase, the integration phase and the sample phaseare defined as:

N _(reset) =kT*C _(F)+4*kT*BW*(1/g _(m) _(—) _(in))*C _(S) ²  (2)

N _(int)=4*kT/C _(COMP) *β*C _(S) ²  (3)

N _(adc) =C _(F) ² *V _(N) ²  (4)

where, T is temperature, k is Boltzmann constant, g_(m) _(—) _(in) istransconductance of the primary transconductor 110 and BW is a bandwidthof the secondary transconductor 140 which is used for compensating theoffset associated with the primary transconductor 110. V_(N) is a noiseof the ADC 150. Also,

β=C _(F)/(C _(F) +C _(S))  (5)

C _(COMP) =C _(C) +C _(F) *C _(S)/(C _(F) +C _(S))  (6)

As illustrated in the above equations, the total noise of the circuit100 is reduced if a value of the feedback capacitor C_(F) 112 isreduced. In one example, an output of the integrator 115 swigs 4 volts.Hence for 200 pC range, a value of the feedback capacitor C_(F) 112 is25 pF and a value of the associated capacitance Cs 106 is 30 pF.

FIG. 2 illustrates a circuit 200, according to an embodiment. Thecircuit 200 includes a photodiode 202, an integrator 215, a comparator230, a secondary transconductor 240, a switched capacitor network 225and an analog to digital converter (ADC) 250. The photodiode 202includes a sensor 204 and an associated capacitance Cs 206. Theintegrator 215 is coupled to the photodiode 202.

The integrator 215 includes a primary transconductor 210 with aninverting terminal 214 and a non-inverting terminal 216. The photodiode202 is coupled to the inverting terminal 214 of primary transconductor210. A non-inverting terminal 216 of the primary transconductor 210 iscoupled to a ground terminal.

A feedback capacitor C_(F) 212 is coupled between the inverting terminal214 and a first output terminal 218 of the primary transconductor 210.In one version, the feedback capacitor C_(F) 212 is also coupled to asecondary reference voltage signal Vrefs 236 and a ground terminalthrough switches. The ADC 250 is coupled across the feedback capacitorC_(F) 212 through a third switch S3 252 and a fourth switch S4 254.

The compensation capacitor Cc 222 is coupled to the first outputterminal 218 of the primary transconductor 210. In one example, thecompensation capacitor Cc 222 is coupled to the secondary referencevoltage signal Vrefs 236 through a switch.

The secondary transconductor 240 receives the secondary referencevoltage signal Vrefs 236 at a first input terminal 244. A second inputterminal 246 of the secondary transconductor 240 is coupled to a firstcapacitor C_(A) 242. The other end of first capacitor C_(A) 242 iscoupled to the ground terminal. The second input terminal 246 is coupledto an output terminal 248 of the secondary transconductor 240 through afifth switch S5 245. The output terminal 248 of the secondarytransconductor 240 is coupled to the first output terminal 218 of theprimary transconductor 210.

A comparator 230 is coupled to the integrator 215. A first invertingterminal 234 of the comparator 230 is coupled to the first outputterminal 218 of the primary transconductor 210. A first non-invertingterminal 232 of the comparator 230 receives a primary reference voltagesignal Vrefp 238. The comparator 230 also receives an enable signal EN235.

A switched capacitor network 225 is coupled across the integrator 215.The switched capacitor network 225 is coupled between the invertingterminal 214 and the first output terminal 218 of the primarytransconductor 210. The switched capacitor network 225 includes a firstinput switch S1 226, a first output switch S2 228 and a primarycapacitor Cp 224 coupled between the first input switch S1 226 and thefirst output switch S2 228.

The first input switch S1 226 is coupled to the inverting terminal 214of the primary transconductor 210. The first output switch S2 228 iscoupled to the first output terminal 218 of the primary transconductor210. The circuit 200 may include one or more additional components knownto those skilled in the relevant art and are not discussed here forsimplicity of the description.

The operation of the circuit 200 illustrated in FIG. 2 is explained now.The photodiode 202 receives light and generates a corresponding currentsignal. The sensor 204 receives the light and the associated capacitanceCs 206 stores a charge corresponding to the received light. The circuit200 operates in a reset phase, an integration phase and a sample phase.

In the beginning, all the switches (the first switch S1 226, the secondswitch S2 228, the third switch S3 252, the fourth switch S4 254 and thefifth switch S5 245) are in open state. In the reset phase, the fifthswitch S5 245 is closed. The inverting terminal 214 of the primarytransconductor 210 is coupled to the ground terminal. An offsetassociated with the primary transconductor 210 will result in a currentflowing from the first output terminal 218 of the primary transconductor210 to the first capacitor C_(A) 242.

A corresponding voltage develops at the second input terminal 246 of thesecondary transconductor 240 and is stored in the first capacitor C_(A)242. Thus, the offset associated with the primary transconductor 210 isstored at an input of the secondary transconductor 240.

The feedback capacitor C_(F) 212 is charged to the secondary referencevoltage signal Vrefs 236. Also, the compensation capacitor Cc 222 ischarged to the secondary reference voltage signal Vrefs 236. The primarycapacitor Cp 224 in the switched capacitor network 225 is charged to theprimary reference voltage signal Vrefp 238.

In the integration phase, the photodiode 202 generates the currentsignal based on the received light. The integrator 215 receives thecurrent signal from the photodiode 202 at the inverting terminal 214 ofthe primary transconductor 210. In one version, the integrator 215receives the current signal from a device coupled to the integrator 215.

The integrator 215 generates an integrated signal at the first outputterminal 218 of the primary transconductor 210. The secondarytransconductor 240 compensates the offset associated with the primarytransconductor 210. The integrator 215 integrates the current signal onthe feedback capacitor C_(F) 212. The feedback capacitor C_(F) 212discharges through the photodiode 202. In one version, the feedbackcapacitor C_(F) 212 and the compensation capacitor Cc 222 both dischargethrough the photodiode 202. The compensation capacitor Cc 222 reducesthe noise of the circuit 200.

The comparator 230 receives the integrated signal from the integrator215. The comparator 230 is activated by the enable signal EN 235 for adefined time period. In one example, the defined time period (T) iscomputed as:

$\begin{matrix}{T = \frac{{Vrefs} - {Vrefp}}{2 \times {Vrefs}}} & (7)\end{matrix}$

The comparator 230 compares the integrated signal and the primaryreference voltage signal Vrefp 238. If the integrated signal is belowthe primary reference voltage signal Vrefp 238 during the defined timeperiod, the comparator 230 generates a feedback signal 256. The feedbacksignal 256 activates the switched capacitor network 225. The feedbacksignal 256 activates the first input switch S1 226 and the first outputswitch S2 228. Thus, the primary capacitor Cp 224 is coupled in parallelto the feedback capacitor C_(F) 212.

As the primary capacitor Cp 224 is charged to the primary referencevoltage signal Vrefp 238 in the reset phase, addition of the primarycapacitor Cp 224 in the circuit 200 does not introduce any glitch at theinverting terminal 214 and the non-inverting terminal 216 of the primarytransconductor 210. This ensures that the current signal from thephotodiode 202 is not affected by addition of the primary capacitor Cp224.

If the integrated signal is above the primary reference voltage signalVrefp 238 during the defined time period, the comparator 230 does notgenerate the feedback signal 256 and hence, the first input switch S1226 and the first output switch S2 228 are not activated. In oneversion, when the terminal of the comparator 230 are interchanged, then,if the integrated signal is above the primary reference voltage signalVrefp 238 during the defined time period, the comparator 230 generatesthe feedback signal 256, to activate the first input switch S1 226 andthe first output switch S2 228. At the end of integration phase, avoltage across the feedback capacitor C_(F) 212 is a sampled voltage.

In the sample phase, the third switch S3 252 and the fourth switch S4254 are closed, while other switches are in open state. The ADC 250measures the sampled voltage across the feedback capacitor C_(F) 212.The ADC 250 generates a digital signal 260 from the sample voltage.

As discussed in connection with circuit 100, illustrated in FIG. 1, thetotal noise of the circuit is reduced if a value of the feedbackcapacitor C_(F) is reduced. This is also illustrated in equations 1 to6. The circuit 200 provides a low value of the feedback capacitor C_(F)212. In one example, the feedback capacitor C_(F) 212 is 4 pF. Thus, inthe integration phase, initially only the feedback capacitor C_(F) 212discharges through the photodiode 202.

The integrator 215 generates the integrated signal, and when theintegrated signal is below the primary reference voltage signal Vrefp238, the primary capacitor Cp 224 also starts discharging through thephotodiode 202. Thus, the current signal is integrated at the feedbackcapacitor C_(F) 212 and the primary capacitor Cp 224.

In one example, the secondary reference voltage signal Vrefs 236 is lessthan the primary reference voltage signal Vrefp 238. Since, in the resetphase, the feedback capacitor C_(F) 212 is charged to the secondaryreference voltage signal Vrefs 236, when the primary capacitor Cp 224 iscoupled in parallel to the feedback capacitor C_(F) 212, a potentialacross both these capacitors is equal to the secondary reference voltagesignal Vrefs 236. Thus, a voltage glitch at the inverting terminal 214of the primary transconductor 210 is very low.

When a level of the current signal is low, the comparator 230 does notgenerate the feedback signal 256, and thus, only the feedback capacitorC_(F) 212 is part of the circuit 200 in integration phase. Thisdrastically reduces a noise of a system using the circuit 200. Thecircuit 200, in one embodiment, is used in a data acquisition system toprovide variable gain to each detector of the plurality of detectorsbased on the received current signal.

FIG. 3 is a timing diagram to illustrate the operation of the circuit200, according to an embodiment. The timing diagram illustrates a resetphase 302, an integration phase 304 and a sample phase 308. The timingdiagram is explained in connection with the circuit 200 illustrated inFIG. 2.

During the reset phase 302, the inverting terminal 214 of the primarytransconductor 210 is coupled to the ground terminal. An offsetassociated with the primary transconductor 210 will result in a currentflowing from the first output terminal 218 of the primary transconductor210 to the first capacitor C_(A) 242.

A corresponding voltage develops at the second input terminal 246 of thesecondary transconductor 240 and is stored in the first capacitor C_(A)242. Thus, the offset associated with the primary transconductor 210 isstored at an input of the secondary transconductor 240.

Also, in the reset phase 302, the feedback capacitor C_(F) 212 ischarged to the secondary reference voltage signal Vrefs 236. Also, thecompensation capacitor Cc 222 is charged to the secondary referencevoltage signal Vrefs 236. The primary capacitor Cp 224 in the switchedcapacitor network 225 is charged to the primary reference voltage signalVrefp 238.

In the integration phase 304, the photodiode 202 generates the currentsignal based on the received light. The integrator 215 receives thecurrent signal from the photodiode 202 at the inverting terminal 214 ofthe primary transconductor 210. In one version, the integrator 215receives the current signal from a device coupled to the integrator 215.

The integrator 215 generates an integrated signal at the first outputterminal 218 of the primary transconductor 210. The secondarytransconductor 240 compensates the offset associated with the primarytransconductor 210. The integrator 215 integrates the current signal onthe feedback capacitor C_(F) 212. The feedback capacitor C_(F) 212discharges through the photodiode 202. In one version, the feedbackcapacitor C_(F) 212 and the compensation capacitor Cc 222 both dischargethrough the photodiode 202.

The comparator 230 receives the integrated signal from the integrator215. The comparator 230 is activated by an enable 306 similar to enablesignal EN 235 for a defined time period (T). In one example, the definedtime period (T) is computed as:

$\begin{matrix}{T = \frac{{Vrefs} - {Vrefp}}{2 \times {Vrefs}}} & (8)\end{matrix}$

The comparator 230 compares the integrated signal and the primaryreference voltage signal Vrefp 238. If the integrated signal is belowthe primary reference voltage signal Vrefp 238 during the defined timeperiod, the comparator 230 generates a feedback signal 256. The feedbacksignal 256 activates the switched capacitor network 225. The feedbacksignal 256 activates the first input switch S1 226 and the first outputswitch S2 228. Thus, the primary capacitor Cp 224 is coupled in parallelto the feedback capacitor C_(F) 212.

If the integrated signal is above the primary reference voltage signalVrefp 238 during the defined time period, the comparator 230 does notgenerate the feedback signal 256 and hence, the first input switch S1226 and the first output switch S2 228 are not activated. In the samplephase 308, the third switch S3 252 and the fourth switch S4 254 areclosed, while other switches are in open state. The ADC 250 measures asampled voltage across the feedback capacitor C_(F) 212. The ADC 250generates a digital signal 260 from the sample voltage.

FIG. 4 is a graph to illustrate the operation of the circuit 200,according to an embodiment. The graph is explained in connection withthe circuit 200 illustrated in FIG. 2. The graph illustrates an enablesignal EN 235. The enable signal EN 235 activates the comparator 230 fora defined time period (T). In one example, the defined time period (T)is computed as:

$\begin{matrix}{T = \frac{{Vrefs} - {Vrefp}}{2 \times {Vrefs}}} & (9)\end{matrix}$

In the reset phase, the feedback capacitor C_(F) 212 is charged to thesecondary reference voltage signal Vrefs 236, and the primary capacitorCp 224 in the switched capacitor network 225 is charged to the primaryreference voltage signal Vrefp 238.

In the integration phase, the feedback capacitor C_(F) 212 startsdischarging through the photodiode 202. Graph A illustrates discharge ofthe feedback capacitor C_(F) 212. At the beginning of the integrationphase (or end of reset phase), the feedback capacitor C_(F) 212 ischarged to the secondary reference voltage signal Vrefs 236. Thus, theintegrated signal is equal to the secondary reference voltage signalVrefs 236. The comparator 230 compares the integrated signal and theprimary reference voltage signal Vrefp 238.

As illustrated in Graph A, the integrated signal is above the primaryreference voltage signal Vrefp 238 during the defined time period (T).Thus, the comparator 230 does not generate the feedback signal 256 andhence, the first input switch S1 226 and the first output switch S2 228are not activated.

Graph B illustrates a case when the integrated signal is below theprimary reference voltage signal Vrefp 238 during the defined timeperiod (T). The comparator 230 generates a feedback signal 256. Thefeedback signal 256 activates the switched capacitor network 225. Thus,the primary capacitor Cp 224 is coupled in parallel to the feedbackcapacitor C_(F) 212.

The graph B illustrates a change in slope when it reaches the primaryreference voltage signal Vrefp 238. This is because when the primarycapacitor Cp 224 is coupled in parallel to the feedback capacitor C_(F)212, and hence, both discharge through the photodiode 202.

FIG. 5 illustrates a circuit 500, according to an embodiment. Thecircuit 500 includes a photodiode 502, an integrator 515, a secondarytransconductor 540, and an analog to digital converter (ADC) 550. Thecircuit 500 includes one or more comparators illustrated as a firstcomparator 530 a, a second comparator 530 b and an Nth comparator 530 n.The circuit 500 also includes one or more switched capacitor networksillustrated as a first switched capacitor network 525 a, a secondswitched capacitor network 525 b and an Nth switched capacitor network525 n.

The photodiode 502 includes a sensor 504 and an associated capacitanceCs 506. The integrator 515 is coupled to the photodiode 502. Theintegrator 515 includes a primary transconductor 510 with an invertingterminal 514 and a non-inverting terminal 516. The photodiode 502 iscoupled to the inverting terminal 514 of primary transconductor 510. Anon-inverting terminal 516 of the primary transconductor 510 is coupledto a ground terminal.

A feedback capacitor C_(F) 512 is coupled between the inverting terminal514 and a first output terminal 518 of the primary transconductor 510.In one version, the feedback capacitor C_(F) 512 is also coupled to asecondary reference voltage signal Vrefs 536 and a ground terminalthrough switches. The ADC 550 is coupled across the feedback capacitorC_(F) 512 through a third switch S3 552 and a fourth switch S4 554.

The compensation capacitor Cc 522 is coupled to the first outputterminal 518 of the primary transconductor 510. In one example, thecompensation capacitor Cc 522 is coupled to the secondary referencevoltage signal Vrefs 536 through a switch.

The secondary transconductor 540 receives the secondary referencevoltage signal Vrefs 536 at a first input terminal 544. A second inputterminal 546 of the secondary transconductor 540 is coupled to a firstcapacitor C_(A) 542. The other end of first capacitor C_(A) 542 iscoupled to the ground terminal. The second input terminal 546 is coupledto an output terminal 548 of the secondary transconductor through afifth switch S5 545. The output terminal 548 of the secondarytransconductor 540 is coupled to the first output terminal 518 of theprimary transconductor 510.

One or more comparators (530 a, 530 b till 530 n) are coupled to theintegrator 515. The one or more comparator includes the first comparator530 a, the second comparator 530 b and the Nth comparator 530 n. A firstinverting terminal of each comparator of the one or more comparators iscoupled to the first output terminal 518 of the primary transconductor510. A first non-inverting terminal of the first comparator 530 areceives a first primary reference voltage signal Vrefp1 538 a. One ormore comparators (530 a, 530 b till 530 n) also receive one or moreprimary reference voltage signals.

A first non-inverting terminal of the second comparator 530 b receives asecond primary reference voltage signal Vrefp2 538 b. Similarly, a firstnon-inverting terminal of the Nth comparator 530 n receives an Nthprimary reference voltage signal Vrefpn 538 n. Each comparator alsoreceives an enable signal. For example, the first comparator 530 areceives an enable signal EN 535 a, and the second comparator 530 breceives an enable signal EN 535 b.

One or more switched capacitor networks are coupled across theintegrator 515. The switched capacitor networks are coupled between theinverting terminal 514 and the first output terminal 518 of the primarytransconductor. One or more switched capacitor networks include a firstswitched capacitor network 525 a, a second switched capacitor network525 b and an Nth switched capacitor network 525 n.

Each of the switched capacitor network of the one or more switchedcapacitor network includes a first input switch, a first output switchand a primary capacitor Cp coupled between the first input switch andthe first output switch. The first input switch is coupled to theinverting terminal 514 of the primary transconductor 510. The firstoutput switch is coupled to the first output terminal 518 of the primarytransconductor 510.

For example, the first switched capacitor network 525 a includes a firstinput switch S1 a, a first primary capacitor Cp1 524 a and a firstoutput switch S2 a. Similarly, the second switched capacitor network 525b includes a first input switch S1 b, a second primary capacitor Cp2 524b and a first output switch S2 b. The circuit 500 may include one ormore additional components known to those skilled in the relevant artand are not discussed here for simplicity of the description.

The operation of the circuit 500 illustrated in FIG. 5 is explained now.The operation of the circuit 500 is explained in connection with thefirst comparator 530 a and the second comparator 530 b only. Similarly,the first switched capacitor network 525 a and the second switchedcapacitor network 525 b are used for depicting the operation of thecircuit 500. This eases the understanding of the operation of thecircuit 500, and is understood not to limit the scope of the presentdisclosure.

The photodiode 502 receives light and generates a corresponding currentsignal. The sensor 504 receives the light and the associated capacitanceCs 506 stores a charge corresponding to the received light. The circuit500 operates in a reset phase, an integration phase and a sample phase.

In the beginning, all the switches are in open state. In the resetphase, the fifth switch S5 545 is closed. The inverting terminal 514 ofthe primary transconductor 510 is coupled to the ground terminal. Anoffset associated with the primary transconductor 510 will result in acurrent flowing from the first output terminal 518 of the primarytransconductor 510 to the first capacitor C_(A) 542.

A corresponding voltage develops at the second input terminal 546 of thesecondary transconductor 540 and is stored in the first capacitor C_(A)542. Thus, the offset associated with the primary transconductor 510 isstored at an input of the secondary transconductor 540.

The feedback capacitor C_(F) 512 is charged to the secondary referencevoltage signal Vrefs 536. Also, the compensation capacitor Cc 522 ischarged to the secondary reference voltage signal Vrefs 536. The firstprimary capacitor Cp1 524 a in the first switched capacitor network 525a is charged to the first primary reference voltage signal Vrefp1 538 a.Similarly, the second primary capacitor Cp2 524 b in the second switchedcapacitor network 525 b is charged to the second primary referencevoltage signal Vrefp2 538 b

In the integration phase, the photodiode 502 generates the currentsignal based on the received light. The integrator 515 receives thecurrent signal from the photodiode 502 at the inverting terminal 514 ofthe primary transconductor 510. In one version, the integrator 515receives the current signal from a device coupled to the integrator 515.

The integrator 515 generates an integrated signal at the first outputterminal 518 of the primary transconductor 510. The secondarytransconductor 540 compensates the offset associated with the primarytransconductor 510. The integrator 515 integrates the current signal onthe feedback capacitor C_(F) 512. The feedback capacitor C_(F) 512discharges through the photodiode 502. In one version, the feedbackcapacitor C_(F) 512 and the compensation capacitor Cc 522 both dischargethrough the photodiode 502.

One or more comparators receive the integrated signal from theintegrator 515. Each comparator is activated by the enable signal EN fora defined time period. For example, the first comparator 530 a isactivated by the enable signal EN 535 a for a first defined time period.In one example, the first defined time period (T1) is computed as:

$\begin{matrix}{{T\; 1} = \frac{{Vrefs} - {{Vrefp}\; 1}}{2 \times {Vrefs}}} & (10)\end{matrix}$

Similarly, the second comparator 530 b is activated by the enable signalEN 535 b for a second defined time period. In another example, thesecond defined time period (T2) is computed as:

$\begin{matrix}{{T\; 1} = \frac{{Vrefs} - {{Vrefp}\; 2}}{2 \times {Vrefs}}} & (11)\end{matrix}$

In one version, Vrefp2 is greater than Vrefp1. One or more comparators(530 a, 530 b till 530 n) generate one or more feedback signals (556 a,556 b till 556 n). The first comparator 530 a compares the integratedsignal and the first primary reference voltage signal Vrefp1 538 a. Ifthe integrated signal is below the first primary reference voltagesignal Vrefp1 538 a during the first defined time period (T1), the firstcomparator 530 a generates a feedback signal 556 a. The feedback signal556 a activates the first switched capacitor network 525 a. The feedbacksignal 556 a activates the first input switch S1 a and the first outputswitch S2 a. Thus, the first primary capacitor Cp1 524 a is coupled inparallel to the feedback capacitor C_(F) 512.

If the integrated signal is above the first primary reference voltagesignal Vrefp1 538 a during the first defined time period (T1), the firstcomparator 530 a does not generate the feedback signal 556 a and hence,the first input switch S1 a and the first output switch S2 a are notactivated.

The second comparator 530 b compares the integrated signal and thesecond primary reference voltage signal Vrefp2 538 b. If the integratedsignal is below the second primary reference voltage signal Vrefp2 538 bduring the second defined time period (T2), the second comparator 530 bgenerates a feedback signal 556 b. The feedback signal 556 b activatesthe second switched capacitor network 525 b. The feedback signal 556 bactivates the first input switch S1 b and the first output switch S2 b.Thus, the second primary capacitor Cp2 524 b is coupled in parallel tothe feedback capacitor C_(F) 512.

If the integrated signal is above the second primary reference voltagesignal Vrefp2 538 b during the second defined time period (T2), thesecond comparator 530 b does not generate the feedback signal 556 b andhence, the first input switch S1 b and the first output switch S2 b arenot activated.

At the end of integration phase, a voltage across the feedback capacitorC_(F) 522 is a sampled voltage. In the sample phase, the third switch S3552 and the fourth switch S4 554 are closed, while other switches are inopen state. The ADC 550 measures the sampled voltage across the feedbackcapacitor C_(F) 522. The ADC 550 generates a digital signal 560 from thesample voltage.

As discussed in connection with circuit 100, illustrated in FIG. 1, thetotal noise of the circuit is reduced if a value of the feedbackcapacitor C_(F) is reduced. This is also illustrated in equations 1 to6. The circuit 500 provides a low value of the feedback capacitor C_(F)512. In one example, the feedback capacitor C_(F) 512 is 4 pF. Thus, inthe integration phase, initially only the feedback capacitor C_(F) 512discharges through the photodiode 502.

The integrator 515 generates the integrated signal, and when theintegrated signal is below the first primary reference voltage signalVrefp1 538 a, the first primary capacitor Cp1 524 a Cp1 also startsdischarging through the photodiode 502. Thus, the current signal isintegrated at the feedback capacitor C_(F) 512 and the first primarycapacitor Cp1 524 a.

If the integrated signal goes even below the second primary referencevoltage signal Vrefp2 538 b, the second primary capacitor Cp2 524 b alsostarts discharging through the photodiode 502. Thus, the current signalis integrated at the feedback capacitor C_(F) 512, the first primarycapacitor Cp1 524 a and the second primary capacitor Cp2 524 b.

When a level of the current signal is low, the comparator 530 does notgenerate the feedback signal, and thus, only the feedback capacitorC_(F) 512 is part of the circuit 500 in integration phase. Thisdrastically reduces a noise of a system using the circuit 500. Thecircuit 500, in one embodiment, is used in a data acquisition system toprovide variable gain to each detector of the plurality of detectorsbased on the received current signal.

FIG. 6 illustrates a method for generating a digital signal from acurrent signal, according to an embodiment. At step 602, a primarycapacitor is charged to a primary reference voltage signal. Asillustrated in circuit 200, the primary capacitor Cp 224 in the switchedcapacitor network 225 is charged to the primary reference voltage signalVrefp 238.

At step 604, a feedback capacitor coupled across a primarytransconductor is charge to a secondary reference voltage signal. Thefeedback capacitor C_(F) 212, in circuit 200, is charged to thesecondary reference voltage signal Vrefs 236. At step 606, an offsetassociated with the primary transconductor is compensated. In oneversion, the offset associated with the primary transconductor is nottaken into account or the step 606 is not performed.

At step 608, a current signal on the feedback capacitor is integrated togenerate an integrated signal. In one example, the integrator integratesthe current signal on the feedback capacitor. At step 610, theintegrated signal is compared with the primary reference voltage signal.

A feedback signal is generated if the integrated signal is below theprimary reference voltage signal during a defined time period, at step612. The defined time period, in an example, is a function of theprimary reference voltage signal and the secondary reference voltagesignal. At step 614, a switched capacitor network is activated by thefeedback signal. The switched capacitor network is coupled across theprimary transconductor.

The switched capacitor network includes a primary capacitor. When thefeedback signal activates the switched capacitor network, the primarycapacitor is coupled in parallel to the feedback capacitor. Thus,initially when the current signal is low, only the feedback capacitor isused for integration. As the current signal increases, the currentsignal is integrated by both the primary capacitor and the feedbackcapacitor.

After integration, a voltage across the feedback capacitor is a samplevoltage. A digital signal is generated from the sampled voltage. In oneexample, the ADC generates the digital signal from the sampled voltage.

FIG. 7 illustrates an imaging system 700, according to an embodiment.The imaging system 700, in one version, is CT a (computed tomography)imaging system. The imaging system 700 includes a gantry 702 thatreceives a patient. The gantry 702 rotates at a defined speed. In oneexample, a controller provides the defined speed to the gantry 702.

An x-ray source 704 is disposed in the gantry 702. The x-ray source 704emits x-rays towards the patient. Many scans are taken progressively asthe patient/object is gradually passed through the gantry. Across-section of the gantry is enlarged and illustrated for betterclarity. The cross-section includes a scintillator 708 and a pluralityof detectors 710. The scintillator 708 receives x-rays attenuated by thepatient. The scintillator 708 generates light from the receivedattenuated x-rays.

A plurality of detectors 710 is coupled to the scintillator 708. Theplurality of detectors 710 includes detectors 710 a and 710 b. At leastone detector of the plurality of detectors 710 include a photodiode andthe circuit 200 (illustrated in FIG. 2). The photodiode generates acurrent signal in response to the received light from the scintillator708. The circuit 200 is coupled to the photodiode and generates adigital signal, similar to the digital signal 260, based on the currentsignal received from the photodiode.

The image reconstructor 720 receives the digital signal from eachdetector of the plurality of detectors 710 to create an image of a partof patient which is being scanned by the imaging system 700. The imagereconstructor 720, in one example, includes a processor. The processorcan be, for example, a CISC-type (Complex Instruction Set Computer) CPU,RISC-type CPU (Reduced Instruction Set Computer), or a digital signalprocessor (DSP). The image reconstructor 720, in one example, isdisposed outside the imaging system 700.

The circuit 200 provides that a variable gain is provided in eachdetector of the plurality of detectors 710 based on the current signalgenerated by the photodiode. This reduces the noise of the imagingsystem 700 drastically. The imaging system 700 may include one or moreadditional components known to those skilled in the relevant art and arenot discussed here for simplicity of the description.

The foregoing description sets forth numerous specific details to conveya thorough understanding of the invention. However, it will be apparentto one skilled in the art that the invention may be practiced withoutthese specific details. Well-known features are sometimes not describedin detail in order to avoid obscuring the invention. Other variationsand embodiments are possible in light of above teachings, and it is thusintended that the scope of invention not be limited by this DetailedDescription, but only by the following Claims.

What is claimed is:
 1. A circuit comprising: an integrator configured togenerate an integrated signal in response to a current signal; acomparator coupled to the integrator and configured to receive theintegrated signal and a primary reference voltage signal, the comparatorconfigured to generate a feedback signal; and a switched capacitornetwork coupled across the integrator, wherein the feedback signal isconfigured to activate the switched capacitor network.
 2. The circuit ofclaim 1, wherein the comparator is configured to receive an enablesignal, the enable signal configured to activate the comparator for adefined time period.
 3. The circuit of claim 1, wherein the integratorcomprises: a primary transconductor configured to receive the currentsignal at an inverting terminal, and configured to generate theintegrated signal at a first output terminal; a non-inverting terminalof the primary transconductor is coupled to a ground terminal; and afeedback capacitor coupled between the inverting terminal and the firstoutput terminal of the primary transconductor.
 4. The circuit of claim 1further comprising a secondary transconductor configured to receive asecondary reference voltage signal, and an output terminal of thesecondary transconductor is coupled to the first output terminal of theprimary transconductor.
 5. The circuit of claim 1 further comprising ananalog to digital converter (ADC) coupled across the feedback capacitor.6. The circuit of claim 1, wherein the switched capacitor network iscoupled between the inverting terminal and the first output terminal ofthe primary transconductor.
 7. The circuit of claim 1, the switchedcapacitor network comprises: a first input switch coupled to theinverting terminal of the primary transconductor; a first output switchcoupled to the first output terminal of the primary transconductor; anda primary capacitor coupled between the first input switch and the firstoutput switch, wherein the first input switch and the first outputswitch are activated by the feedback signal.
 8. The circuit of claim 1is configured to operate in a reset phase, an integration phase and asample phase.
 9. The circuit of claim 1, wherein in the reset phase: theprimary capacitor is charged to the primary reference voltage signal;the feedback capacitor is charged to the secondary reference voltagesignal; and the inverting terminal of the primary transconductor iscoupled to the ground terminal such that an offset associated with theprimary transconductor is stored at an input of the secondarytransconductor.
 10. The circuit of claim 1, wherein in the integrationphase: the integrator receives the current signal at the invertingterminal of the primary transconductor, and generates the integratedsignal; the secondary transconductor compensates the offset associatedwith the primary transconductor; the comparator is activated by theenable signal for the defined time period; and the comparator comparesthe integrated signal and the primary reference voltage signal, whereinif the integrated signal is below the primary reference voltage signalduring the defined time period, the feedback signal is generated by thecomparator to activate the first input switch and the first outputswitch.
 11. The circuit of claim 1, wherein in the sample phase the ADCis configured to measure a sampled voltage across the feedbackcapacitor, the ADC is configured to generate a digital signal from thesampled voltage.
 12. A circuit comprising: an integrator configured togenerate an integrated signal in response to a current signal; one ormore comparators coupled to the integrator and configured to receive theintegrated signal and one or more primary reference voltage signals, theone or more comparators configured to generate one or more feedbacksignals; and one or more switched capacitor networks coupled across theintegrator, the one or more switched capacitor networks are activated bythe one or more feedback signals.
 13. The circuit of claim 12, whereinthe integrator comprises: a primary transconductor configured to receivethe current signal at an inverting terminal, and configured to generatethe integrated signal at a first output terminal; a non-invertingterminal of the primary transconductor is coupled to a ground terminal;and a feedback capacitor coupled between the inverting terminal and thefirst output terminal of the primary transconductor.
 14. The circuit ofclaim 12, wherein each switched capacitor network of the one or moreswitched capacitor networks comprises: a first input switch coupled tothe inverting terminal of the primary transconductor; a first outputswitch coupled to the first output terminal of the primarytransconductor; and a primary capacitor coupled between the first inputswitch and the first output switch, wherein the first input switch andthe first output switch are activated by a feedback signal of the one ormore feedback signals.
 15. A method comprising: charging a primarycapacitor to a primary reference voltage signal; charging a feedbackcapacitor coupled across a primary transconductor to a secondaryreference voltage signal; compensating an offset associated with theprimary transconductor; integrating a current signal on the feedbackcapacitor to generate an integrated signal; comparing the integratedsignal with the primary reference voltage signal; generating a feedbacksignal if the integrated signal is below the primary reference voltagesignal during a defined time period; and activating a switched capacitornetwork by the feedback signal, wherein the switched capacitor networkis coupled across the primary transconductor.
 16. The method of claim15, wherein the switched capacitor network comprises: a first inputswitch coupled to an inverting terminal of the primary transconductor; afirst output switch coupled to a first output terminal of the primarytransconductor; and a primary capacitor coupled between the first inputswitch and the first output switch, wherein the first input switch andthe first output switch are activated by the feedback signal.
 17. Themethod of claim 15 further comprising: measuring a sampled voltageacross the feedback capacitor; and generating a digital signal from thesampled voltage.
 18. An imaging system comprising: a gantry configuredto receive a patient, the gantry is configured to rotate at a definedspeed; an x-ray source disposed in the gantry and configured to emitx-rays towards the patient; a scintillator configured to receive x-raysattenuated by the patient, the scintillator is configured to generatelight from the received attenuated x-rays; and a plurality of detectorscoupled to the scintillator, at least one detector of the plurality ofdetectors comprising: a photodiode configured to generate a currentsignal in response to received light; an integrator coupled to thephotodiode and configured to generate an integrated signal in responseto the current signal received from the photodiode; a comparator coupledto the integrator and configured to receive the integrated signal and aprimary reference voltage signal, the comparator configured to generatea feedback signal; and a switched capacitor network coupled across theintegrator, wherein the feedback signal is configured to activate theswitched capacitor network.
 19. The imaging system of claim 18, whereinthe detector further comprises an analog to digital converter (ADC)coupled across the feedback capacitor.
 20. The imaging system of claim18, wherein the switched capacitor network comprises: a first inputswitch coupled to an inverting terminal of the primary transconductor; afirst output switch coupled to a first output terminal of the primarytransconductor; and a primary capacitor coupled between the first inputswitch and the first output switch, wherein the first input switch andthe first output switch are activated by the feedback signal.